[内容简介]
This book focuses on the automated design of microfluidic-based biochips for large-scale bioassays and safety-critical applications. Digital Microfluidic Biochips describes a new generation of biochips that offer dynamic reconfigurability, system scalability, system integration, and defect and fault tolerance. The authors present a system-level design automation framework that addresses key issues in the design, analysis, and testing of digital microfluidic biochips. Topics include: operation scheduling, resource binding, and module placement; test resource optimization and fault detection while running normal bioassays; and reconfiguration-based techniques designed to increase the yield and dependability of digital microfluidic biochips.
Table of Contents
PART I
SYNTHESIS TECHNIQUES
Introduction
Technology Issues
Digital Microfluidic Biochips
Microfluidic Biochip Design Challenges
Book Outline
Architectural-Level Synthesis
Background
High-Level Synthesis Methodology
Simulation Experiments
Module Placement
Background
Module Placement Problem
Fault Tolerance for Digital Microfluidic Biochips
Experimental Evaluation
Unified Synthesis Methodology
Problem Formulation
PRSA-Based Algorithm
Enhancement for Defect Tolerance
Experimental Evaluation
Droplet Routing
Background
Problem Formulation
Routing Method
Experimental Evaluation
PART II
TESTING TECHNIQUES
Test Methodology
Background
Classification of Faults
Unified Detection Mechanism
Parametric Fault Testing
Simulation Experimental Setup
Test Planning
Problem Definition
Analysis of Computational Complexity
Integer Linear Programming Model for OPP
Heuristic Algorithms
Simulation Results
Concurrent Testing
Concurrent Testing Methodology
Optimal Scheduling for Concurrent Testing
Concurrent Testing Example
Defect-Oriented Testing and Diagnosis
Fault Modeling
Defect-Oriented Experiment
Testing and Diagnosis
Real-Life Application
PART III
RECONFIGURATION TECHNIQUES
Reconfiguration Schemes
Proposed Reconfiguration Schemes
Example Evaluation
Defect Tolerance Based on Space Redundancy
Background
Microfluidic Array with Hexagonal Electrodes
Defect-Tolerant Designs
Estimation of Yield Enhancement
Evaluation Example
Defect Tolerance Based on Graceful Degradation
Tile-Based Architecture
Clustered Defect Model
Graceful Degradation with Reconfiguration
Simulation Results
Conclusions and Future Work
Contributions of the Book
Future Work
Bibliography
Index
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