超大规模集成电路设计中的高级模型降阶法
Book Description
Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to advanced 'state-of-the-art' MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.
About the Author
Sheldon X.-D. Tan is an associate professor in the Department of Electrical Engineering, and cooperative faculty member in the Department of Computer Science and Engineering, at the University of California, Riverside. He received his PhD in electrical and computer engineering in 1999 from the University of Iowa, Iowa City. His current research interests focus on design automation for VLSI integrated circuits. Lei He is an associate professor in the Department of Electrical Engineering at the University of California, Los Angeles, where he was also awarded his PhD in computer science in 1999. His current research interests include computer-aided design of VLSI circuits and systems.
Contents v
Figures viii
Tables xiv
Foreword xv
Acknowledgments xvii
1 Introduction 1
1.1 The need for compact modeling of interconnects 1
1.2 Interconnect analysis and modeling methods in a nutshell 2
1.3 Book outline 4
1.4 Summary 7
2 Projection-based model order reduction algorithms 8
2.1 Moments and moment-matching methods 8
2.2 Moment computation in MNA formulation 11
2.3 Asymptotic waveform evaluation 13
2.4 Projection-based model order reduction methods 20
2.5 Numerical examples 32
2.6 Historical notes 32
2.7 Summary 34
2.8 Appendices 34
3 Truncated balanced realization methods for MOR 37
3.1 Introduction 37
3.2 The singular value decomposition (SVD) 38
3.3 Proper orthogonal decomposition (POD) 38
3.4 Classic truncated balanced realization methods 39
3.5 Passive-preserving truncated balanced realization methods 43
3.6 Hybrid TBR and combined TBR-Xrylov subspace methods 45
3.7 Empirical TBR and poor man's TBR 45
3.8 Computational complexities of TBR methods 47
3.9 Practical implementation and numerical issues 48
3.10 Numerical examples 53
3.11 Summary 54
4 Passive balanced truncation of linear systems in descriptor form 56
4.1 Introduction 56
4.2 The passive balanced truncation algorithm: PriTBR 57
4.3 Structure-preserved balanced truncation 60
4.4 Numerical examples 62
4.5 Summary 64
5 Passive hierarchical model order reduction 67
5.1 Overview of hierarchical MOR algorithm 68
5.2 DDD-based hierarchical decomposition 70
5.3 Hierarchical reduction versus moment-matching 76
5.4 Preservation of reciprocity 80
5.5 Multi-point expansion hierarchical reduction 81
5.6 Numerical examples 84
5.7 Summary 91
5.8 Historical notes on node-elimination-based reduction methods 91
6 Terminal reduction of linear dynamic circuits 93
6.1 Review of the SVDMOR method 95
6.2 Input and output moment matrices 96
6.3 The extended-SVDMOR (ESVDMOR) method 99
6.4 Determination of cluster number by SVD 102
6.5 K-means clustering algorithm 104
6.6 TermMerg algorithm 106
6.7 Numerical examples 111
6.8 Summary 116
7 Vector-potential equivalent circuit for inductance modeling 118
7.1 Vector-potential equivalent circuit 119
7.2 VPEC via PEEC inversion 124
7.3 Numerical examples 128
7.4 Inductance models in hierarchical reduction 131
7.5 Summary 136
8 Structure-preserving model order reduction 137
8.1 Introduction 137
8.2 Chapter overview 138
8.3 Background 139
8.4 Block-structure-preserving model reduction 141
8.5 TBS method 144
8.6 Two-level analysis 149
8.7 Numerical examples 151
8.8 Summary 157
9 Block structure-preserving reduction for RLCK circuits 158
9.1 Introduction 158
9.2 Block structure-preserving model reduction 159
9.3 Structure preservation for admittance transfer-function matrices 161
9.4 General block structure-preserving MOR method 163
9.5 Numerical examples 167
9.6 Summary 169
9.7 Appendix 170
10 Model optimization and passivity enforcement 172
10.1 Passivity enforcement 172
10.2 Model optimisation for active circuits 176
10.3 Optimization for magnitude and phase responses 178
10.4 Numerical examples 181
10.5 Summary 185
11 General multi-port circuit realization 187
11.1 Review of existing circuit-realization methods 187
11.2 General multi-port network realization 195
11.3 Multi-port non-reciprocal circuit realization 197
11.4 Numerical examples 199
11.5 Summary 203
12 Reduction for multi-terminal interconnect circuits 204
12.1 Introduction 204
12.2 Problems of subspace projection-based MOR methods 205
12.3 Model order reduction for multiple-terminal circuits: MTermMOR 208
12.4 Numerical examples 212
12.5 Summary 214
13 Passive modeling by signal waveform shaping 215
13.1 Introduction 215
13.2 Passivity and positive-realness 217
13.3 Conditional passivity and positive-realness 218
13.4 Passivity enforcement by waveform shaping 221
13.5 Numerical examples 225
13.6 Summary 226
References 229
Index 238
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