[内容简介]
At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture
In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.
[目次]
List of Figures
List of Tables
Preface
Acknowledgments
Introduction
Down to the Wire
Routing Problems
Flat Routing Framework
Sequential Approach
Concurrent Approach
Hierarchical Routing Framework
Top-Down Hierarchical Approach
Bottom-Up Hierarchical Approach
Hybrid Hierarchical Approach
Multilevel Routing Framework
Previous Multilevel Routing Framework
Our Multilevel Routing Framework
Organization of the Book
Multilevel Routing Framework
Multilevel Full-Chip Routing Considering Crosstalk and Performance
Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
Multilevel Full-Chip Routing for the X-Based Architecture
Routing Challenges for Nanometer Technology
Routing Requirement for the Nanometer Era
Signal-Integrity Problems
Crosstalk Problems
Process Antenna Effects
Manufacturability Problems
Optical Proximity Correction
Phase Shift Masking
Double Via Insertion
X-Architecture
Multilevel Full-Chip Routing Considering Crosstalk and Performance
Introduction
Elmore Delay Model
Multilevel Routing Framework
Performance-Driven Routing Tree Construction
Crosstalk-Driven Layer/Track Assignment
Experimental Results
Summary
Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
Introduction
Antenna Effect Damage
Multilevel Routing Framework
Bottom-Up Optimal Jumper Prediction
Multilevel Routing with Antenna Avoidance
Experimental Results
Summary
Multilevel Full-Chip Routing for the X-Based Architecture
Introduction
Multilevel X-Routing Framework
X-Architecture Steiner Tree Construction
Three-Terminal Net Routing Based on X-Architecture
X-Steiner Tree Algorithm by Delaunay Triangulation
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Summary
Concluding Remarks and Future Work
Multilevel Routing Framework
Routing Challenges for Nanometer Technology
Multilevel Full-Chip Routing Considering Crosstalk and Performance
Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
Multilevel Full-Chip Routing for the X-Based Architecture
Future Research Directions
References
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