Power Efficiency in Broadband Wireless Communications

[BOOK DESCRIPTION]

Power Efficiency in Broadband Wireless Communications focuses on the improvement of power efficiency in wireless communication systems, especially of mobile devices. Reviewing cutting-edge techniques for conserving power and boosting power efficiency, the book examines various technologies and their impact on consumer devices. It considers each technology, first by introducing the main physical layer components in recent wireless communication systems along with their shortcomings, and then proposing solutions for overcoming these shortcomings. The book covers orthogonal frequency division multiplexing (OFDM) signal generation and formulation and examines the advantages and disadvantages of OFDM systems compared to alternative multiplexing. It introduces one of the main drawbacks of OFDM systems, peak-to-average power ratio (PAPR), and discusses several PAPR techniques. It also explains how to overcome the main drawbacks of real-world OFDM system applications. * Considers power amplifier linearization for increasing power efficiency and reducing system costs and power dissipation * Describes the implementation scenario of the most promising linearization technique, digital predistortion * Presents some experimental demonstrations of digital predistortion when the device under test is in the loop Because the most costly device in a communication system that has a direct impact on power efficiency and power consumption is the power amplifier, the book details the behavior and characteristics of different classes of power amplifiers. Describing the evolution of the mobile cellular communication system, it details a cost-effective technique to help you increase power efficiency, reduce system costs, and prolong battery life in next generation mobile devices.

[TABLE OF CONTENTS]

Preface                                            xi
Chapter 1 Evolution Of Multiplexing Techniques     1  (10)
In Wireless Communications Systems
  1.1 Introduction                                 1  (1)
  1.2 Evolution of Mobile Cellular Networks        2  (2)
    1.2.1 First-Generation Cellular Systems        2  (1)
    1.2.2 Second-Generation Cellular Systems       3  (1)
    1.2.3 Third-Generation Cellular Systems        3  (1)
    1.2.4 Future Broadband Wireless                4  (1)
    Communication
  1.3 Evolution of Multiplexing Techniques         4  (4)
    1.3.1 Frequency Division Multiplexing          4  (2)
    Access (FDMA) Technique
    1.3.2 Time Division Multiplexing Access        6  (1)
    (TDMA) Technique
    1.3.3 Code Division Multiple Access (CDMA)     6  (1)
    Technique
    1.3.4 Orthogonal Frequency Division            6  (1)
    Multiplexing (OFDM) in 4G
    1.3.4.1 OFDM Pros and Cons                     7  (1)
  1.4 Key Technologies                             8  (2)
    1.4.1 Generalized Frequency Division           8  (1)
    Multiplexing (GFDM)
    1.4.2 Multiple Input Multiple Output (MIMO)    8  (2)
    1.4.3 Space Time and Space Frequency           10 (1)
    Transmission over MIMO Networks
  1.5 Summary                                      10 (1)
  References                                       10 (1)
Chapter 2 Orthogonal Frequency Division            11 (12)
Multiplexing Theory
  2.1 Introduction                                 11 (1)
  2.2 History of OFDM                              12 (1)
  2.3 OFDM Blocks                                  13 (2)
  2.4 OFDM Mathematical Analysis and               15 (4)
  Measurements
  2.5 Summary                                      19 (2)
  References                                       21 (2)
Chapter 3 Power Amplifiers In Wireless             23 (36)
Communications
  3.1 Introduction                                 23 (2)
  3.2 High Power Amplifiers                        25 (2)
    3.2.1 Nonlinearity of Power Amplifiers         25 (2)
  3.3 Characteristics of Power Amplifiers          27 (7)
    3.3.1 Efficiency                               27 (1)
      3.3.1.1 Drain Efficiency                     28 (1)
      3.3.1.2 Power-Added Efficiency (PAE)         28 (1)
    3.3.2 Output Power                             28 (1)
    3.3.3 Signal Gain                              29 (1)
    3.3.4 Trade-Off between Linearity and          29 (2)
    Efficiency
    3.3.5 Power Amplifier Two-Tone Test            31 (3)
  3.4 Classification of Power Amplifiers           34 (10)
    3.4.1 Class A                                  35 (3)
    3.4.2 Class B                                  38 (1)
    3.4.3 Class AB                                 39 (1)
    3.4.4 Class C                                  39 (2)
    3.4.5 Class F                                  41 (3)
    3.4.6 Other High-Efficiency Classes            44 (1)
  3.5 Power Amplifier Memory Effects               44 (6)
    3.5.1 Electrical Memory Effects                45 (1)
    3.5.2 Electrothermal Memory Effects            46 (1)
    3.5.3 Modeling Power Amplifiers                46 (1)
    3.5.4 Modeling Power Amplifiers without        46 (2)
    Memory
    3.5.5 Power Amplifier Model with Memory        48 (2)
    Effects
  3.6 Power Amplifier Simulations                  50 (6)
  3.7 Summary                                      56 (1)
  References                                       57 (2)
Chapter 4 Peak-To-Average Power Ratio              59 (82)
  4.1 Introduction                                 59 (6)
  4.2 The Effect of High PAPR on Power             65 (4)
  Amplifiers
  4.3 PAPR Reduction Techniques                    69 (25)
    4.3.1 Distortion-Based PAPR Reduction          71 (3)
    Techniques
      4.3.1.1 Clipping Method                      71 (2)
      4.3.1.2 Windowing Method                     73 (1)
      4.3.1.3 Companding Method                    73 (1)
    4.3.2 Distortionless-Based PAPR Reduction      74 (19)
    Methods
      4.3.2.1 Coding Method                        74 (1)
      4.3.2.2 Active Constellation Extension       75 (1)
      4.3.2.3 Partial Transmit Sequence            76 (1)
      4.3.2.4 Enhanced PTS                         77 (3)
      4.3.2.5 Selected Mapping Method              80 (6)
      4.3.2.6 Tone Reservation Method              86 (1)
      4.3.2.7 Dummy Signal Insertion Method        86 (3)
      4.3.2.8 DSI-PTS                              89 (1)
      4.3.2.9 DSI-EPTS                             90 (3)
    4.3.3 A Discussion on the Current PAPR         93 (1)
    Reduction Solutions
  4.4 Design of the Proposed DSI-SLM Scheme        94 (11)
    4.4.1 The Proposed DSI-SLM Scheme              95 (6)
    4.4.2 DSI-SLM Computational Complexity         101(4)
  4.5 Simulation Results and Analysis              105(10)
  4.6 Results Discussion                           115(2)
  4.7 The Optimum Phase Sequence with the Dummy    117(14)
  Sequence Insertion Scheme
    4.7.1 Design of the OPS-DSI Scheme             117(8)
    4.7.2 System Performance of the OPS-DSI        125(17)
    Scheme
      4.7.2.1 OPS-DSI Side Information             125(1)
      4.7.2.2 Advantages and Disadvantages of      126(1)
      the Proposed OPS-DSI Scheme
      4.7.2.3 OPS-DSI Computational Complexity     126(1)
      4.7.2.4 Simulation Results and Analysis      127(3)
      4.7.2.5 Results Discussion                   130(1)
  4.8 Summary                                      131(1)
  References                                       132(9)
Chapter 5 Peak-To-Average Power Ratio              141(44)
Implementation
  5.1 Introduction                                 141(1)
  5.2 Software Implementation Design               142(2)
    5.2.1 MATLAB Simulation Design                 143(1)
    5.2.2 C++ Implementation Design                143(1)
    5.2.3 Implementation Platform                  143(1)
  5.3 Hardware Complexity                          144(2)
  5.4 Hardware Implementation                      146(3)
  5.5 Field Programmable Gate Array                149(2)
    5.5.1 The System Generator Tool                150(1)
    5.5.2 System Generator Design Flow             150(1)
  5.6 The Prototype of the Dummy Signal            151(11)
  Insertion with Selected Mapping Scheme
    5.6.1 The Inverse Fast Fourier Transform       151(2)
    Prototype
    5.6.2 Using Acce1DSP Software to Prototype     153(2)
    IFFT
    5.6.3 Prototype of the Conventional            155(1)
    Selected Mapping Method
    5.6.4 Implementation of the DSI-SLM Scheme     156(2)
    5.6.5 Hardware Resource Consumption            158(4)
  5.7 FPGA Implementation of the Optimum Phase     162(11)
  Sequence with the Dummy Sequence Insertion
  Scheme
    5.7.1 Implementation of the OPS-DSI            163(5)
    Transmitter
    5.7.2 Implementation of the OPS-DSI Receiver   168(5)
  5.8 Implementation of Complex Division in the    173(8)
  Receiver
    5.8.1 Newton-Raphson Division                  174(1)
    5.8.2 Error Analysis                           175(1)
    5.8.3 Initial Approximation Techniques         175(1)
    5.8.4 Hardware Structure of the Complex        176(1)
    Divider
    5.8.5 Divisor Scaling                          177(1)
    5.8.6 Newton-Raphson Method                    177(1)
    5.8.7 Postscaling of Division Values           178(3)
  5.9 Hardware Resource Consumption of the         181(1)
  OPS-DSI Scheme
  5.10 Summary                                     181(1)
  References                                       182(3)
Chapter 6 Power Amplifier Linearization            185(42)
  6.1 Introduction                                 185(4)
  6.2 Power Amplifier Linearization Techniques     189(22)
    6.2.1 The Feedback Linearization Technique     189(1)
    6.2.2 Linear Amplification with Nonlinear      190(1)
    Components
    6.2.3 Feedforward Linearizers                  191(1)
    6.2.4 Predistortion Linearizers                192(1)
    6.2.5 Digital Predistortion                    192(3)
    6.2.6 Memory Polynomial Predistortion          195(1)
    6.2.7 Complex Gain Predistortion               196(6)
    6.2.8 The Digital Predistortion                202(1)
    Linearization Method
    6.2.9 Complex Gain Memory Predistortion        203(8)
  6.3 Simulation Results of Applying Complex       211(12)
  Gain Memory Predistortion
  6.4 Summary                                      223(1)
  References                                       224(3)
Chapter 7 Digital Predistortion Implementation     227(24)
  7.1 Introduction                                 227(1)
  7.2 Simulation with Xilinx Blocksets             227(1)
    7.2.1 System Generator                         228(1)
  7.3 Xilinx Embedded Development Kit              228(1)
  7.4 Field Programmable Gate Array                229(2)
    7.4.1 Description                              230(1)
    7.4.2 Functional Description                   231(1)
  7.5 Complex Gain Memory Predistortion            231(3)
  Implementation
    7.5.1 Complex Multiplier                       232(1)
    7.5.2 Lookup Table (LUT)                       233(1)
  7.6 Complex Divider Implementation               234(2)
  7.7 Results of FPGA Implementation               236(3)
  7.8 Digital Signal Processing Implementation     239(1)
  of Digital Predistortion
  7.9 DP Block Design                              239(10)
    7.9.1 Linear Convergence Adaptation            241(2)
    Algorithm
    7.9.2 Adaptation Block                         243(1)
    7.9.3 Complex Multiplier                       244(1)
    7.9.4 Saleh Model Amplifier                    245(1)
    7.9.5 The IQ512 Block                          246(3)
  7.10 Summary                                     249(1)
  References                                       250(1)
Chapter 8 Experimental Results                     251(16)
  8.1 Introduction                                 251(1)
  8.2 Experimental Setup                           251(5)
  8.3 Experimental Results                         256(2)
  8.4 Comparison between Simulation and            258(6)
  Experimental Results
  8.5 Summary                                      264(1)
  References                                       264(3)
Appendix A: Complex Baseband Representation Of     267(6)
Band-Pass Signals
Appendix B                                         273(36)
Index                                              309